Semi-Methodology

Souletics Software · Semiconductor Engineering

From Disruptive Idea
to Tapeout

End-to-end semiconductor physical design — from VHDL concept through schematic capture, custom layout, full-chip integration, and tapeout signoff. 20 years at Intel. Schematic to silicon. Every step.

AI Accelerators Memory Design CPU & GPU Security Chips Custom Logic Mixed-Signal 180nm → 5nm
Chip Categories Served
🧠

AI Accelerators

NPU, TPU, inference engine silicon

💾

Memory

SRAM, HBM-adjacent, embedded memory

⚡

CPU & GPU

High-performance compute silicon

🔐

Security Chips

Cryptography, secure enclave silicon

📡

RF & Mixed-Signal

Analog, RF, mixed-signal custom blocks

🏭

Full-Chip SoC

System-on-chip integration & signoff

Design for Manufacturability — Front End First

Wire length, wire width, spacing rules, and abutment constraints should all be determined at the front end — before physical implementation begins. DFM violations discovered late in the flow cost time, mask money, and yield. Our methodology embeds manufacturability constraints from the first schematic pass, eliminating the costly late-stage iterations that plague most physical design programs.

The Engineering Design Flow

01
Concept & Architecture — VHDL
VHDL Verilog SystemVerilog

Every chip starts with a disruptive idea. Architecture is defined in hardware description language — VHDL or Verilog — capturing the intended behavior of every block before a single transistor is placed. This is where AI accelerator architecture, security chip algorithms, and memory subsystem behavior are formally specified. DFM constraints are embedded here — wire budget, block sizing, critical path targets.

RTL specification Block partitioning Power budgeting DFM targets set Critical path analysis
02
Schematic Capture
Cadence Virtuoso Synopsys Custom Compiler

RTL behavior is translated into circuit-level schematics — transistor-accurate representations of every cell, block, and interconnect. For digital blocks, synthesis maps RTL to standard cell netlists. For analog and custom blocks, hand-crafted schematics define transistor sizing, bias networks, and signal paths. This is where digital meets analog and where custom logic is born.

Digital synthesis Analog schematic Cell characterization Netlist generation Pre-layout simulation
03
Custom Layout — Digital & Analog
Cadence Virtuoso Layout Synopsys IC Compiler Mentor Calibre

Physical implementation of every cell and block. Custom digital layout — full-custom transistor-level implementation of critical path cells, memory bitcells, and high-performance logic. Analog layout — precision placement of matched devices, guard rings, shielding, and substrate contacts to minimize noise and parasitics. Wire length and wire width targets established in front end are enforced here. Abutment compatibility verified between adjacent blocks.

Full-custom cell layout Analog precision placement Guard ring implementation Abutment verification Wire width enforcement Parasitic minimization
04
Auto Place & Route (APR) — Full Chip Integration
Cadence Innovus Synopsys ICC2 Cadence Tempus

The full chip comes together. Floorplanning positions every macro and custom block. Power planning delivers clean supply across the die. Placement distributes standard cells. Clock tree synthesis balances skew across every register. Routing connects every net while honoring spacing rules, via enclosures, and density targets. Abutment issues between custom blocks and APR regions are resolved here — this is the integration challenge that separates experienced physical designers from novices.

Floorplanning Power grid design Standard cell placement Clock tree synthesis Global & detailed routing Abutment resolution IR drop analysis
05
Physical Verification — DRC · LVS · ERC
Mentor Calibre nmDRC Calibre nmLVS Synopsys IC Validator

DRC — Design Rule Check: Every polygon on every layer verified against the foundry's PDK design rules. Min width, min spacing, enclosure, extension, fin snap grids, density fill. Zero violations required before tapeout. LVS — Layout vs Schematic: Physical layout extracted and compared against schematic netlist. Shorts, opens, and parameter mismatches identified. LVS clean required. ERC — Electrical Rule Check: Antenna violations, floating nodes, ESD compliance, density uniformity for CMP. All three must pass with zero errors.

DRC — zero violations LVS — clean netlist match ERC — antenna & ESD Density fill Via enclosure check
06
Signoff — Timing · Waveform · Dummification
Cadence Tempus Synopsys PrimeTime Cadence Spectre

Timing signoff at all PVT corners — fast corner (FF, low temp, high voltage) and slow corner (SS, high temp, low voltage). Setup and hold verified across every path. Waveform verification — gate-level simulation with extracted parasitics confirms functional correctness at signal level. Dummification — metal and poly dummy fill added across every layer to meet foundry density requirements for CMP uniformity. This is the final preparation before the GDSII is released.

Fast & slow corner STA Setup & hold closure Gate-level simulation Waveform verification Metal dummification Poly density fill SPEF extraction
✓
Tapeout — GDSII Delivery
GDSII OASIS Foundry PDK

The GDSII file — containing every polygon on every layer of the complete chip — is delivered to the foundry. Masks are cut. Silicon is manufactured. 20+ tapeouts completed at Intel, including a solo cryptography chip tapeout. Every step above has been executed in production, at leading-edge nodes, on real silicon that shipped. That is not a claim. That is a record.

GDSII final release Mask data prep Foundry handoff 20+ Intel tapeouts Solo crypto chip
Industry-Standard Toolsets

Cadence Virtuoso

CADENCE DESIGN SYSTEMS

Custom & analog layout Schematic capture Mixed-signal implementation

Cadence Innovus

CADENCE DESIGN SYSTEMS

Auto place & route Power planning Clock tree synthesis

Cadence Tempus

CADENCE DESIGN SYSTEMS

Static timing analysis Multi-corner signoff Hold & setup closure

Synopsys Design Compiler

SYNOPSYS

RTL to gate synthesis Netlist optimization Timing constraint mapping

Synopsys PrimeTime

SYNOPSYS

Timing signoff PVT corner analysis POCV / AOCV analysis

Mentor Calibre

SIEMENS EDA

DRC — design rule check LVS — layout vs schematic ERC & antenna check

Cadence Spectre

CADENCE DESIGN SYSTEMS

SPICE simulation Analog verification Post-layout simulation

Synopsys IC Validator

SYNOPSYS

Physical verification DRC / LVS signoff Hierarchical checking
Process Nodes Supported

180nm – 65nm

Legacy / Mature

Automotive, industrial, analog, power management. Fully depreciated fabs. Cost-effective and robust.

45nm – 22nm

Mainstream

FinFET introduction. IoT, embedded, mixed-signal. Strong IP ecosystem.

14nm – 10nm

Workhorse

Intel's 14nm era. High-performance compute, server CPUs. Multi-patterning expertise required.

7nm – 5nm

Advanced

EUV lithography. AI chips, mobile SoCs. Highest density and performance.

Ready to start?

Schedule a Technical Consultation

20 years. 20+ tapeouts. Schematic to GDSII.
Bring your chip concept and let's talk about what it takes to get to silicon.

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